Circuit designs are typically written in a register transfer level (RTL) format. To implement the circuit design in hardware, e.g., circuitry, an electronic design automation (EDA) tool converts the RTL into an intermediate representation of the circuit design called a data flow graph (DFG). The DFG representation can be specified as a word-level representation or as a bit-level representation. The DFG defines the circuit architecture of the circuit design that is realized in physical circuitry.
In cases where the DFG includes bit-level assignments within a loop, the word-level representation of the DFG can become cumbersome to use. These problems are further exacerbated when the loop includes a chain of bit-assignments with variables in the bit index expression. This scenario often results in slower runtimes for the EDA tool and an inefficient circuit architecture for implementing the circuit design that requires significant circuit resources and significant area to implement.